This invention relates to a dynamic RAM (Random Access Memory) and a technique effective for use in the formation of a high level stored in a storage capacitor by a stepped-down internal voltage while utilizing a division word line system having main word lines and sub-word lines, for example.
A division word line system provided with a plurality of sub-word lines connected to memory cells with respect to main word lines has been proposed to activate only a necessary memory block provided with a selected memory cell and reduce memory areas to be activated wherever possible to thereby provide less power consumption and to speed up the operation of selecting one of sub-word lines connected to the memory cells. An example of this type of division word line system has been described in U.S. application Ser. No. 08/503,738 (corresponding to Japanese Patent Application Laid-Open No. 1-286197).
Further, a system for forming a pair of PMOS transistors constituting a sense amplifier in a N-well region and supplying an internal step-down or deboosted voltage to the N-well region has been described in Japanese Patent Application Laid-Open Nos. 1-187856 and 2-18784.